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data sheet ics87001bgi-01 revision a january 23, 2013 1 ?2013 integrated device technology, inc. lvcmos/lvttl clock divider ICS87001I-01 general description the ICS87001I-01 is a low skew, 1, 2, 3, 4, 5, 6, 8, 16 lvcmos/lvttl clock divider. the ICS87001I-01 has selectable clock inputs that accept single ended input levels. output enable pin controls whether the output is in the active or high impedance state. the ICS87001I-01 is characterized at 3.3v, 2.5v and mixed 3.3v/2.5v, 3.3v/1.8v, 2.5v/1.8v input/output supply operating modes.guaranteed part-to-part skew characteristics make the ICS87001I-01 ideal for those applications demanding well defined performance and repeatability. features ? one lvcmos / lvttl output ? selectable lvcmos / lvttl clock inputs ? maximum output frequency: 250mhz ? part-to-part skew: 135ps (typical) ? power supply modes: core/output 3.3v/3.3v 3.3v/2.5v 3.3v/1.8v 2.5v/2.5v 2.5v/1.8v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package n output divider n2:n0 0 0 0 1 (default) 001 2 010 3 011 4 100 5 101 6 110 8 111 16 0 1 3 q oe n2:n0 clk1 clk0 clk_sel pulldown pulldown pulldown pulldown pullup 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n0 n1 n2 clk1 clk_sel clk0 v dd oe v ddo nc q nc gnd nc nc gnd pin assignment block diagram ICS87001I-01 16-lead tssop 4.4mm x 5.0mm x 0.925mm package body g package top view
ics87001bgi-01 revision a january 23, 2013 2 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function table table 3. programmable output divider function table number name type description 1 oe input pullup output enable. when low, output is in high impedance state. when high, outputs are active. lvcmos / lvttl interface levels. 2v dd power power supply pin. 3, 5 clk0, clk1 input pulldown single-ended clock inputs. lvcmos/lvttl interface levels. 4 clk_sel input pulldown input clock selection. when high, selects clk1 input. when low, selects clk0 input. lvcmos / lvttl interface levels. 6, 7, 8 n2, n1, n0 input pulldown output divider select pins. lvcmos/lvttl interface levels. see table 3. 9, 12 gnd power power supply ground. 10, 11, 13, 15 nc unused no connect. 14 q output single-ended clock output. lvcmos/lvttl interface levels. 16 v ddo power output supply pin. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance v ddo = 3.465v 6 pf v ddo = 2.625v 5 pf v ddo = 1.95v 5 pf r out output impedance v ddo = 3.3v5% 17 ? v ddo = 2.5v5% 20 ? v ddo = 1.8v0.15v 28 ? inputs n divider value maximum output frequency (mhz) n2 n1 n0 0 0 0 1 (default) 250 0 0 1 2 125 0 1 0 3 83.333 0 1 1 4 62.5 1 0 0 5 50 1 0 1 6 41.667 1 1 0 8 31.25 1 1 1 16 15.625
ics87001bgi-01 revision a january 23, 2013 3 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd =v ddo = 3.3v 5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85c table 4c. power supply dc characteristics, v dd = 3.3v 5%, v ddo =1.8v 0.15v, t a = -40c to 85c table 4d. power supply dc characteristics, v dd =v ddo = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ? ja 100.3 ? c/w (0 mps) storage temperature, t stg -65 ? cto150 ? c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 55 ma i ddo output supply current no load 5 ma symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 55 ma i ddo output supply current no load 5 ma symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 1.65 1.8 1.95 v i dd power supply current 55 ma i ddo output supply current no load 5 ma symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 55 ma i ddo output supply current no load 5 ma
ics87001bgi-01 revision a january 23, 2013 4 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider table 4e. power supply dc characteristics, v dd = 2.5v 5%, v ddo =1.8v 0.15v, t a = -40c to 85c table 4f. lvcmos/lvttl dc characteristics, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information, output load test circuit diagrams. symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 1.65 1.8 1.95 v i dd power supply current 55 ma i ddo output supply current no load 5 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage clk_sel, clk[0:1], n[2:0] v dd = 3.3v -0.3 0.8 v oe v dd = 3.3v -0.3 0.6 v clk_sel, clk[0:1], n[2:0] v dd = 2.5v -0.3 0.7 v oe v dd = 2.5v -0.3 0.5 v i ih input high current clk_sel, clk[0:1], n[2:0] v dd =v in = 3.465v or 2.625v 150 a oe v dd =v in = 3.465v or 2.625v 5 a i il input low current clk_sel, clk[0:1], n[2:0] v dd = 3.465v or 2.625v, v in =0v -5 a oe v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v ddo = 3.3v 2.6 v v ddo = 2.5v 1.8 v v ddo = 1.8v 1.25 v v ol output low voltage; note 1 v ddo = 3.3v 0.5 v v ddo = 2.5v 0.5 v v ddo = 1.8v 0.4 v i ozl output hi-z current low -5 a i ozh output hi-z current high 5a
ics87001bgi-01 revision a january 23, 2013 5 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider ac electrical characteristics table 5a. ac characteristics, v dd =v ddo = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. all parameters measured at f in ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. table 5b. ac characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. all parameters measured at f in ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f out output frequency 250 mhz t pd propagation delay, low to high; note 1 n ? 2 3.6 4.6 5.7 ns n > 2 4.3 5.5 6.7 ns t sk(pp) part-to-part skew; note 2, 3 750 ps t r /t f output rise/fall time 20% to 80% 0.4 0.6 1.0 ns odc output duty cycle 40 60 % t en output enable time 10 ns t dis output disable time 10 ns symbol parameter test conditions minimum typical maximum units f out output frequency 250 mhz t pd propagation delay, low to high; note 1 n ? 2 3.5 4.8 6.2 ns n > 2 4.5 5.7 6.9 ns t sk(pp) part-to-part skew; note 2, 3 590 ps t r /t f output rise/fall time 20% to 80% 0.4 0.7 1.1 ns odc output duty cycle 40 60 % t en output enable time 10 ns t dis output disable time 10 ns
ics87001bgi-01 revision a january 23, 2013 6 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider table 5c. ac characteristics, v dd = 3.3v 5%, v ddo = 1.8v 0.15v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. all parameters measured at f in ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. table 5d. ac characteristics, v dd =v ddo = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. all parameters measured at f in ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f out output frequency 250 mhz t pd propagation delay, low to high; note 1 n ? 2 3.6 5.2 7.0 ns n > 2 4.8 6.2 7.6 ns t sk(pp) part-to-part skew; note 2, 3 680 ps t r /t f output rise/fall time 20% to 80% 0.4 1.0 2.3 ns odc output duty cycle 40 60 % t en output enable time 10 ns t dis output disable time 10 ns symbol parameter test conditions minimum typical maximum units f out output frequency 250 mhz t pd propagation delay, low to high; note 1 n ? 2 3.7 4.9 6.2 ns n > 2 4.5 5.8 7.1 ns t sk(pp) part-to-part skew; note 2, 3 570 ps t r /t f output rise/fall time 20% to 80% 0.4 0.7 1.2 ns odc output duty cycle 40 60 % t en output enable time 10 ns t dis output disable time 10 ns
ics87001bgi-01 revision a january 23, 2013 7 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider table 5e. ac characteristics, v dd = 2.5v 5%, v ddo = 1.8v 0.15v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. all parameters measured at f in ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f out output frequency 250 mhz t pd propagation delay, low to high; note 1 n ? 2 3.6 5.2 7.0 ns n > 2 4.8 6.2 7.7 ns t sk(pp) part-to-part skew; note 2, 3 550 ps t r /t f output rise/fall time 20% to 80% 0.5 1.1 2.5 ns odc output duty cycle 40 60 % t en output enable time 10 ns t dis output disable time 10 ns
ics87001bgi-01 revision a january 23, 2013 8 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider parameter measurement information 3.3v core/3.3v lvcmos output load ac test circuit 3.3v core/1.8v lvcmos output load ac test circuit 2.5v core/1.8v lvcmos output load ac test circuit 3.3v core/2.5v lvcmos output load ac test circuit 2.5v core/2.5v lvcmos output load ac test circuit part-to-part skew scope qx gnd v dd, 1.65v5% -1.65v5% v ddo scope qx gnd v ddo v dd 0.9v0.075v -0.9v0.075v 2.4v0.09v scope qx gnd v ddo v dd 0.9v0.075v -0.9v0.075v 1.6v0.05v scope qx gnd v dd 1.25v5% -1.25v5% v ddo 2.05v5% scope qx gnd v dd, 1.25v5% -1.25v5% v ddo q q t sk(pp) v ddo 2 v ddo 2 part 1 part 2
ics87001bgi-01 revision a january 23, 2013 9 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider parameter measurement information, continued propagation delay output rise/fall time output duty cycle/pulse width/period output enable/disable time applications information recommendations for unused input pins inputs: clk inputs for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a1k ? resistor can be used. t pd v dd 2 v ddo 2 q clk0, clk1 20% 80% 80% 20% t r t f q q t period t pw t period odc = v ddo 2 x 100% t pw v ddo /2 t en t dis v dd /2 v dd /2 v dd v oh 0v v ddo /2 output q oe (high-level enabling)
ics87001bgi-01 revision a january 23, 2013 10 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider power considerations this section provides information on power dissipation and junction temperature for the ICS87001I-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS87001I-01 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max =v dd_max *i dd = 3.465v * 55ma = 190.6mw ? power (output) max =v ddo_max *i ddo = 3.465v * 5ma = 17.3mw lvcmos output power dissipation ? output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out =v dd_max /[2*(50 ? +r out )] = 3.465v / [2 * (50 ? +17 ? )] = 25.9ma ? power dissipation on the r out per lvcmos output power (r out )=r out *(i out ) 2 =17 ? * (25.9ma) 2 = 11.4mw ? total power (r out ) = 11.4m w*1= 11.4mw dynamic power dissipation at f out_max (250mhz) power (250mhz) = c pd * frequency * (v ddo ) 2 = 6pf * 250mhz * (3.465v) 2 = 18mw per output total power (250mhz) = 18m w*1= 18mw total power dissipation ? total power = power (core) max + power (output) max + total power (r out ) + total power (250mhz) = 190.6mw + 17.3mw + 11.4mw + 18mw = 237.3mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 100.3c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.237w * 100.3c/w = 109c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
ics87001bgi-01 revision a january 23, 2013 11 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider table 6. thermal resistance ? ja for 16 lead tssop, forced convection ? ja by velocity meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w
ics87001bgi-01 revision a january 23, 2013 12 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider reliability information table 7. ? ja vs. air flow table for a 16 lead tssop transistor count the transistor count for ICS87001I-01: 2769 package outline and package dimensions package outlin e - g suffix for 16 lead tssop table 8. package dimensions for 16 lead tssop reference document: jedec publication 95, mo-153 ? ja vs. air flow meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
ics87001bgi-01 revision a january 23, 2013 13 ?2013 integrated device technology, inc. ICS87001I-01 data sheet lvcmos/lvttl clock divider ordering information table 9. ordering information part/order number marking package shipping packaging temperature 87001bgi-01lf 001bi01l ?lead-free? 16 lead tssop tube -40c to 85c 87001bgi-01lft 001bi01l ?lead-free? 16 lead tssop tape & reel -40c to 85c
ICS87001I-01 data sheet lvcmos/lvttl clock divider disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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